In some digital audio implementations, a user must recover a clock of a complex input signal, such as digital audio data, so that the input signal may be correctly processed during subsequent operations. Generally, a phase lock loop circuit is used to determine the frequency of the clock. When a phase lock loop circuit is used, a reference clock that approximates the clock frequency of the input signal is provided to the phase lock loop circuit. The phase lock loop circuit then uses an iterative process in which the clock frequency of the input signal is compared with a reference frequency. By comparing the unknown clock frequency to a reference frequency, the reference frequency may be adjusted to more closely approximate the unknown clock frequency.
In a typical phase lock loop circuit, an incoming signal is provided to a phase detector such that the frequency of the incoming signal may be approximated. In the phase detector, the frequency of the incoming signal is compared with a reference frequency to produce a relative phase signal. The relative phase signal output by the phase detector is subsequently provided to a filter to provide a smoothly varying control output from the intermittent adjustments to the relative phase signal. The filtered signal is provided as an input to a voltage controlled oscillator (VCO). The VCO then uses the output of the phase lock loop circuit to adjust the reference frequency to more closely approximate the unknown clock frequency of the input signal. The process is performed iteratively such that the VCO may more closely approximate the unknown clock frequency with each successive iteration.
Although phase lock loop circuits generally perform well in most digital audio implementations, several limitations do exist. For example, when the input signal is a complex data stream without a perfectly periodic signal, the phase lock loop circuit is generally not able to lock to the frequency of the data stream. A complex data stream may be a digital audio data stream which is transmitted in a standard format such as AES-EBU or CP-340. The AES-EBU and CP-340 formats include preambles, digital audio data and digital non-audio data which do not allow the phase lock loop circuit to easily find a periodic edge to lock to.
When receiving such complex data streams, a "pre-processing" circuit must be provided to receive and process the data stream before it is input to the phase lock loop circuit. The pre-processing circuit is implemented to isolate a periodic edge within the complex data stream. Subsequently, the periodic edge is provided as control to enable the phase lock loop circuit to be able to lock to the frequency of the input signal. Pre-processing is, therefore, required to recover a reference frequency clock signal with little jitter.
Additionally, for the pre-processing circuit to function correctly, a reference frequency provided for comparison by the voltage controlled oscillator must be within a relatively close range of the clock signal of the complex data stream. If the reference frequency is not within a close range of the clock signal of the complex data stream, the pre-processing system is not able to work correctly. Therefore, the recovered clock signal will typically have too much jitter and will not provide the phase lock loop circuit with a usable input signal. Additionally, when the reference frequency provided by the voltage controlled oscillator is within a close range of the clock signal, the voltage controlled oscillator is designed to operate at only one sampling frequency. To operate at a wider range of sampling frequencies, a plurality of phase lock loop circuits would be required wherein each of the plurality of phase lock loop circuits has a voltage controlled oscillator designed to detect one of a plurality of sampling frequencies. The circuitry required to implement such a system would be too expensive and require too much circuit area to implement in most communications systems.